Buffer memory address converter, sector address information reliability judging device , defective sector Judging device, ecc block synchronization detectior , optical disk reproducing device ,medium,and grogram

ABSTRACT

To provide an optical disk drive having an enhanced replaying capability in case of an abnormality occurring in various kinds of synchronization of the optical disk drive or in replay of a defective sector.  
     A frame synchronization counter value address translation decoder  202,  low order ID address translation decoder  203,  adder/subtracter  204,  high order ID address translation decoder  205,  and adder  206  are used to translate information read from an optical disk medium into an absolute storage address in a storage medium, and thus data that is highly replayed can be stored in the storage medium.

TECHNICAL FIELD

[0001] The present invention relates to a buffer memory addresstranslation device that generates a data storage address in a buffermemory used for an error correction processing of data read from anoptical disk and data transfer to a host computer, a sector addressreliability determination device that processes sector addressinformation of data read from an optical disk, a defective sectordetermination device that determines a defective sector of an opticaldisk, an ECC block synchronization detection device that detects asynchronization of ECC blocks of data read from an optical disk, anoptical disk drive, a medium, and an information aggregate.

BACKGROUND ART

[0002] In a conventional optical disk drive, as disclosed in JapanesePatent Laid-Open No. 10-302402 and Japanese Patent Laid-Open No.11-162105, generation of a data storage address in a buffer memory thatis storage means used for an error correction processing of data readfrom an optical disk and data transfer to a host computer is carried outin the following manner.

[0003] That is, detection and interpolation of various synchronizationpatterns indicating a beginning of data structure (ECC blocksynchronization, sector synchronization, frame synchronization) arecarried out, and the data storage address in the buffer memory iscontrolled according to the various synchronization detection andinterpolation signals.

[0004] That is, the address generation has been carried out in such amanner that the number of various synchronization detection andinterpolation signals is reflected as is in the data storage address inthe buffer memory.

[0005] Furthermore, in order to prevent an abnormality from occurring inthe data storage address in the buffer memory, the detection andinterpolation of the various synchronization signals have been enhanced.

[0006] In the case where such an optical disk drive is used that thenumber of the various synchronization detection and interpolationsignals corresponds to the data storage address in the buffer memory asdescribed above, there has been a problem that the correspondencebetween pieces of data stored in the buffer memory is lost before andafter the abnormality in the synchronization signals by an abnormalityoccurring in the synchronization detection and interpolation signals,such as omission or error in detection, or failed interpolation, that iscaused by factors such as a fingerprint or scratch on the optical diskmedium.

[0007] That is, there is a problem (first problem) that when anabnormality is caused in the synchronization detection and interpolationsignals by factors such as a fingerprint or scratch on the optical diskmedium, the correspondence between pieces of data stored in the buffermemory is lost.

[0008] Furthermore, there has been a problem that if the correspondencebetween pieces of data stored in the buffer memory is lost by theabove-described factors, the data read from the optical disk medium isdifficult to be properly replayed even with error correcting means.

[0009] That is, there is a problem (second problem) that if thecorrespondence between pieces of data stored in the buffer memory islost by the above-described factors, the data read from the optical diskmedium is difficult to be properly replayed even with error correctingmeans.

[0010] In addition, there has been a problem that in case of the opticaldisk medium having defective sector information recorded therein, therehas been a problem that it is difficult to read data from the opticaldisk medium unless the defective sector information is acquired from theoptical disk medium and the defective sector is indicated.

[0011] That is, there is a problem (third problem) that in case of theoptical disk medium having defective sector information recordedtherein, there has been a problem that it is difficult to read data fromthe optical disk medium unless the defective sector information isacquired from the optical disk medium and the defective sector isindicated.

DISCLOSURE OF THE INVENTION

[0012] In view of the above-described first problem, the presentinvention aims to provide a buffer memory address translation device, asector address information reliability determination device, a defectivesector determination device, an ECC block synchronization detectiondevice, an optical disk drive, a medium, and program with which thecorrespondence between pieces of data stored in the buffer memory is notlost even if an abnormality occurs in the synchronization detection andinterpolation signals due to factors such as a fingerprint or scratch.

[0013] In view of the above-described second problem, the presentinvention aims to provide a buffer memory address translation device, asector address information reliability determination device, a defectivesector determination device, an ECC block synchronization detectiondevice, an optical disk drive, a medium, and program with which thecorrespondence between pieces of data stored in the buffer memory is notlost.

[0014] In view of the above-described third problem, the presentinvention aims to provide a buffer memory address translation device, asector address information reliability determination device, a defectivesector determination device, an ECC block synchronization detectiondevice, an optical disk drive, a medium, and program with which data canbe read from the optical disk medium without the need for acquiring thedefective sector information from the optical disk medium.

[0015] To solve the problems described above, the 1st invention of thepresent invention (corresponding to claim 1) is a buffer memory addresstranslation device, characterized in that the buffer memory addresstranslation device comprises:

[0016] analysis means of analyzing a synchronization pattern included indata read from an optical disk medium and positional data allowing adata position to be recognized included in the data read from saidoptical disk medium; and

[0017] address generation means of generating an address for storageinto a buffer memory based on a result of said analysis, and

[0018] said read data is stored in a region corresponding to saidgenerated address in said buffer memory.

[0019] The 2nd invention of the present invention (corresponding toclaim 2) is the buffer memory address translation device according tothe 1st invention, characterized in that said positional data is sectoraddress information.

[0020] The 3rd invention of the present invention (corresponding toclaim 3) is the buffer memory address translation device according tothe 1st invention, characterized in that said positional data is a framesynchronization code.

[0021] The 4th invention of the present invention (corresponding toclaim 4) is the buffer memory address translation device according tothe 2nd invention, characterized in that said analysis means comprises:

[0022] sector address information readout means of reading sectoraddress information included in the data read from said optical diskmedium;

[0023] sector address information reliability determination means ofdetermining the reliability of said read sector address information;

[0024] sector address information interpolation means of interpolatingsaid sector address information for a sector the sector addressinformation for which is not determined to be reliable; and

[0025] sector address information selection means of selecting saidsector address information read by said sector address informationreadout means or said sector address information interpolated by saidsector address information interpolation means according to apredetermined criterion, and

[0026] said address generation means generates an address for storageinto said buffer memory according to said selected sector addressinformation.

[0027] The 5th invention of the present invention (corresponding toclaim 5) is the buffer memory address translation device according tothe 4th invention, characterized in that said read sector addressinformation has an error detection code added thereto, and saiddetermination of reliability is accomplished by using said added errordetection code to detect an error in said read sector addressinformation.

[0028] The 6th invention of the present invention (corresponding toclaim 6) is the buffer memory address translation device according tothe 4th invention, characterized in that said determination ofreliability is accomplished by determining continuity between said readsector address information and sector address information previouslyread.

[0029] The 7th invention of the present invention (corresponding toclaim 7) is the buffer memory address translation device according tothe 4th invention, characterized in that said predetermined criterion isa criterion of reliability required by external control means, and

[0030] said sector address information selection means selects one ofthem by analyzing the criterion of reliability required by said externalcontrol means and said determination result of said sector addressinformation reliability determination means.

[0031] The 8th invention of the present invention (corresponding toclaim 8) is a buffer memory address translation device, characterized inthat the buffer memory address translation device comprises:

[0032] readout means of reading a frame synchronization code added todata read from an optical disk medium;

[0033] storage means of encoding said read frame synchronization codesand sequentially storing the same therein;

[0034] frame position digitization means of digitizing a position of aframe based on an arrangement of said codes stored in said storagemeans;

[0035] continuity determination means of determining whether saiddigitized frame positions are continuous;

[0036] counter means of counting the number of the digitized framepositions that are determined to be continuous;

[0037] frame position determination means of comparing the number of thecontinuous frame positions counted by said counter means with athreshold that can be set by an external control means and, if theresult of said comparison satisfies a predetermined condition,determining that the value digitized by said frame position digitizationmeans is a frame position;

[0038] frame position interpolation means of, if the condition is notsatisfied in said frame position determination means, carrying outinterpolation based on a previous frame position for which the conditionis satisfied to find a frame position; and

[0039] address generation means of generating an address for storageinto a buffer memory based on said frame position found by said frameposition interpolation means or the frame position determined by saidframe position determination means, and

[0040] said read data is stored in a region corresponding to saidgenerated address in said buffer memory.

[0041] The 9th invention of the present invention (corresponding toclaim 9) is a sector address information reliability determinationdevice, characterized in that the sector address information reliabilitydetermination device comprises:

[0042] error detection means of detecting an error of sector addressinformation included in data read from an optical disk medium and havingan error detection code added thereto;

[0043] sector address information continuity determination means ofcomparing said sector address information currently extracted from saidread data with said sector address information previously extracted todetermine the continuity of said sector address information; and

[0044] reliability determination means of determining the reliability ofsaid sector address information based on the result of the errordetection for said sector address information and the result of thecontinuity determination for said sector address information withreference to a predetermined condition set by said external controlmeans.

[0045] The 10th invention of the present invention (corresponding toclaim 10) is a defective sector determination device, characterized inthat the defective sector determination device comprises:

[0046] continuity detection means of detecting a position where adifference occurs between the continuity of said sector physical addressinformation and the continuity of said sector logical addressinformation;

[0047] defective sector detection means of finding a defective sectorusing said detected difference; and

[0048] informing means of informing an external control means of saiddetected defective sector, in readout from a rewritable optical diskmedium storing sector physical address information that is a physicaladdress of said sector besides sector logical address informationincluded in data.

[0049] The 11th invention of the present invention (corresponding toclaim 11) is the defective sector determination device according to the10th invention), characterized in that said defective sector detectionmeans detects the number of said defective sectors and the sectorphysical address information of a leading one of said defective sectors,and

[0050] said informing means informs of said number of defective sectorsand said sector physical address information of a leading one of saiddefective sectors.

[0051] The 12th invention of the present invention (corresponding toclaim 12) is the defective sector determination device according to the10th invention, characterized in that said continuity determinationmeans comprises:

[0052] sector physical address information readout means of reading saidsector physical address information;

[0053] sector physical address information error detection means ofdetecting an error of said read sector physical address information; and

[0054] sector physical address information comparison means ofcomparing, of the sector physical address information for which an erroris not detected by said sector physical address information errordetection means, current sector physical address information with theprevious sector physical address information, and

[0055] said continuity determination means of, if said sector physicaladdress information error detection means detects no error in said readsector physical address information, determining the continuity betweensaid read sector physical address information and said previous sectorphysical address information based on the result of said comparison.

[0056] The 13th invention of the present invention (corresponding toclaim 13) is the defective sector determination device according to the10th invention, characterized in that said continuity determinationmeans comprises:

[0057] sector logical address information readout means of reading saidsector logical address information;

[0058] sector logical address information error detection means ofdetecting an error of said read sector logical address information; and

[0059] sector logical address information comparison means of comparing,of the sector logical address information for which an error is notdetected by said sector logical address information error detectionmeans, current sector logical address information with the previoussector logical address information, and

[0060] said continuity determination means of, if said sector logicaladdress information error detection means detects no error in said readsector logical address information, determining the continuity betweensaid read sector logical address information and said previous sectorlogical address information based on the result of said comparison.

[0061] The 14th invention of the present invention (corresponding toclaim 14) is the defective sector determination device according to the10th invention, characterized in that said position where a differenceoccurs is a position where there are one or more sectors for which thesector physical address information is determined to be continuousbetween two continuous sectors corresponding to the sector addressinformation for which said sector address information is determined tobe continuous.

[0062] The 15th invention of the present invention (corresponding toclaim 15) is the defective sector determination device according to the11th invention, characterized in that said defective sector detectionmeans regards the sector physical address information of the sector forwhich said sector logical address information is not continuous as thesector physical address information of said leading one of the defectivesectors.

[0063] The 16th invention of the present invention (corresponding toclaim 16) is the defective sector determination device according to the11th invention, characterized in that said defective sector detectionmeans detects the number of sectors for which said sector physicaladdress information is determined to be continuous and that existbetween the two sectors corresponding to the sector logical addressinformation determined to be continuous, and regards said number ofdetected sectors as said number of defective sectors.

[0064] The 17th invention of the present invention (corresponding toclaim 17) is an ECC block synchronization detection device,characterized in that the ECC block synchronization device comprises:

[0065] error detection means of detecting an error of sector addressinformation that is read from an optical disk medium in which an errorcorrecting code is added thereto across n sectors (n=integer) and theerror correcting code is accommodated in the continuous n sectors;

[0066] sector address information division means of, if said errordetection means detects no error in said read sector addressinformation, finding the quotient of said read sector addressinformation divided by the number of sectors constituting an ECC block;and

[0067] ECC block detection means of, if said sector address informationerror detection means detects no error in said read sector addressinformation, comparing said quotient of said read sector addressinformation with the previously found quotient and determining that theECC block synchronization is detected if the comparison does not resultin a match.

[0068] The 18th invention of the present invention (corresponding toclaim 18) is an optical disk drive, characterized in that the opticaldisk drive comprises:

[0069] data readout means of reading data from an optical disk medium;and

[0070] a controller that, in response to a request from an externaldevice, controls said data readout means to temporarily store said readdata into a buffer memory and then transfers the same to said externaldevice, and

[0071] said controller has the buffer address translation device, sectoraddress reliability determination device, defective sector determinationdevice, or ECC block synchronization detection device according to anyof claims 1 to 17 implemented therein.

[0072] The 19th invention of the present invention (corresponding toclaim 19) is a medium capable of being processed by a computer,characterized in that the medium stores a program for making thecomputer serve as whole or part of the analysis means of analyzing asynchronization pattern included in data read from an optical diskmedium and positional data allowing a data position to be recognizedincluded in the data read from said optical disk medium, and

[0073] the address generation means of generating an address for storageinto a buffer memory based on a result of said analysis of the buffermemory address translation device according to the 1st invention.

[0074] The 20th invention of the present invention (corresponding toclaim 20) is a medium capable of being processed by a computer,characterized in that the medium stores a program for making thecomputer serve as whole or part of the readout means of reading a framesynchronization code added to data read from an optical disk medium,

[0075] the storage means of encoding said read frame synchronizationcodes and sequentially storing the same therein,

[0076] the frame position digitization means of digitizing a position ofa frame based on an arrangement of said codes stored in said storagemeans,

[0077] the continuity determination means of determining whether saiddigitized frame positions are continuous,

[0078] the counter means of counting the number of the digitized framepositions that are determined to be continuous,

[0079] the frame position determination means of comparing the number ofthe continuous frame positions counted by said counter means with athreshold that can be set by an external control means and, if theresult of said comparison satisfies a predetermined condition,determining that the value digitized by said frame position digitizationmeans is a frame position,

[0080] the frame position interpolation means of, if the condition isnot satisfied in said frame position determination means, carrying outinterpolation based on a previous frame position for which the conditionis satisfied to find a frame position, and

[0081] the address generation means of generating an address for storageinto a buffer memory based on said frame position found by said frameposition interpolation means or the frame position determined by saidframe position determination means of the buffer memory addresstranslation device according to the 8th invention.

[0082] The 21st invention of the present invention (corresponding toclaim 21) is a medium capable of being processed by a computer,characterized in that the medium stores a program for making thecomputer serve as whole or part of the error detection means ofdetecting an error of sector address information included in data readfrom an optical disk medium and having an error detection code addedthereto,

[0083] the sector address information continuity determination means ofcomparing said sector address information currently extracted from saidread data with said sector address information previously extracted todetermine the continuity of said sector address information, and

[0084] the reliability determination means of determining thereliability of said sector address information based on the result ofthe error detection for said sector address information and the resultof the continuity determination for said sector address information withreference to a predetermined condition set by said external controlmeans of the sector address information reliability determination deviceaccording to the 9th invention.

[0085] The 22nd invention of the present invention (corresponding toclaim 22) is a medium capable of being processed by a computer,characterized in that the medium stores a program for making thecomputer serve as whole or part of the continuity detection means ofdetecting a position where a difference occurs between the continuity ofsaid sector physical address information and the continuity of saidsector logical address information,

[0086] the defective sector detection means of finding a defectivesector using said detected difference, and

[0087] the informing means of informing an external control means ofsaid detected defective sector of the defective sector determinationdevice according to the 10th invention in readout from a rewritableoptical disk medium storing said sector physical address informationthat is a physical address of said sector besides said sector logicaladdress information included in data.

[0088] The 23rd invention of the present invention (corresponding toclaim 23) is a medium capable of being processed by a computer,characterized in that the medium storing a program for making thecomputer serve as whole or part of the error detection means ofdetecting an error of sector address information that is read from anoptical disk medium and has an error correcting code added theretoacross n sectors (n=integer) and the error correcting code accommodatedin the continuous n sectors,

[0089] the sector address information division means of, if said errordetection means detects no error in said read sector addressinformation, finding the quotient of said read sector addressinformation divided by the number of sectors constituting an ECC block,and

[0090] the ECC block detection means of, if said sector addressinformation error detection means detects no error in said read sectoraddress information, comparing said quotient of said read sector addressinformation with the previously found quotient and determining that theECC block synchronization is detected if the comparison does not resultin a match of the ECC block synchronization detection device accordingto the 17th invention.

[0091] The 24th invention of the present invention (corresponding toclaim 24) is a program for making the computer serve as whole or part ofthe analysis means of analyzing a synchronization pattern included indata read from an optical disk medium and positional data allowing adata position to be recognized included in the data read from saidoptical disk medium, and

[0092] the address generation means of generating an address for storageinto a buffer memory based on a result of said analysis of the buffermemory address translation device according to the 1st invention.

[0093] The 25th invention of the present invention (corresponding toclaim 25) is a program for making the computer serve as whole or part ofthe readout means of reading a frame synchronization code added to dataread from an optical disk medium,

[0094] the storage means of encoding said read frame synchronizationcodes and sequentially storing the same therein,

[0095] the frame position digitization means of digitizing a position ofa frame based on an arrangement of said codes stored in said storagemeans,

[0096] the continuity determination means of determining whether saiddigitized frame positions are continuous,

[0097] the counter means of counting the number of the digitized framepositions that are determined to be continuous,

[0098] the frame position determination means of comparing the number ofthe continuous frame positions counted by said counter means with athreshold that can be set by an external control means and, if theresult of said comparison satisfies a predetermined condition,determining that the value digitized by said frame position digitizationmeans is a frame position,

[0099] the frame position interpolation means of, if the condition isnot satisfied in said frame position determination means, carrying outinterpolation based on a previous frame position for which the conditionis satisfied to find a frame position, and

[0100] the address generation means of generating an address for storageinto a buffer memory based on said frame position found by said frameposition interpolation means or the frame position determined by saidframe position determination means of the buffer memory addresstranslation device according to the 8th invention.

[0101] The 26th invention of the present invention (corresponding toclaim 26) is a program for making the computer serve as whole or part ofthe error detection means of detecting an error of sector addressinformation included in data read from an optical disk medium and havingan error detection code added thereto,

[0102] the sector address information continuity determination means ofcomparing said sector address information currently extracted from saidread data with said sector address information previously extracted todetermine the continuity of said sector address information, and

[0103] the reliability determination means of determining thereliability of said sector address information based on the result ofthe error detection for said sector address information and the resultof the continuity determination for said sector address information withreference to a predetermined condition set by said external controlmeans of the sector address information reliability determination deviceaccording to the 9th invention.

[0104] The 27th invention of the present invention (corresponding toclaim 27) is a program for making the computer serve as whole or part ofthe continuity detection means of detecting a position where adifference occurs between the continuity of said sector physical addressinformation and the continuity of said sector logical addressinformation,

[0105] the defective sector detection means of finding a defectivesector using said detected difference, and

[0106] the informing means of informing an external control means ofsaid detected defective sector of the defective sector determinationdevice according to the 10th invention in readout from a rewritableoptical disk medium storing said sector physical address informationthat is a physical address of said sector besides said sector logicaladdress information included in data.

[0107] The 28th invention of the present invention (corresponding toclaim 28) is a program for making the computer serve as whole or part ofthe error detection means of detecting an error of sector addressinformation that is read from an optical disk medium and has an errorcorrecting code added thereto across n sectors (n=integer) and the errorcorrecting code accommodated in the continuous n sectors,

[0108] the sector address information division means of, if said errordetection means detects no error in said read sector addressinformation, finding the quotient of said read sector addressinformation divided by the number of sectors constituting an ECC block,and

[0109] the ECC block detection means of, if said sector addressinformation error detection means detects no error in said read sectoraddress information, comparing said quotient of said read sector addressinformation with the previously found quotient and determining that theECC block synchronization is detected if the comparison does not resultin a match of the ECC block synchronization detection device accordingto the 17th invention.

[0110] Now, an operation of the present invention will be described.

[0111] The optical disk drive according to the present invention ischaracterized in that a synchronization pattern and data enablingrecognition of a data position included in the data read from an opticaldisk medium are analyzed, and the data read from the optical disk mediumis accurately stored in a buffer memory.

[0112] According to the present invention, even if an abnormality in thevarious synchronization detection and interpolation signals is caused byfactors such as a fingerprint or scratch on the optical disk medium, anaccurate data storage address in the buffer memory can be generated, andwhen data is to be read from the optical disk medium having defectivesector information recorded therein, a reliable data storage address inthe buffer memory can be generated without the need for acquiring thedefective sector information before reading the data from the opticaldisk medium.

BRIEF DESCRIPTION OF THE DRAWINGS

[0113]FIG. 1 is a block diagram showing an optical disk drive accordingto a first embodiment of the present invention;

[0114]FIG. 2 is a block diagram for illustrating generation of a datastorage address in a buffer memory according to the first embodiment ofthe present invention;

[0115]FIG. 3 is a block diagram for illustrating a frame processing andsector processing according to the first embodiment of the presentinvention;

[0116]FIG. 4 is a block diagram for illustrating an ECC block processingaccording to the first embodiment of the present invention;

[0117]FIG. 5 is a block diagram showing a frame position detection blockand frame position reliability determination block according to thefirst embodiment of the present invention;

[0118]FIG. 6 is a block diagram for illustrating an ID reliabilitydetermination block according to the first embodiment of the presentinvention;

[0119]FIG. 7 shows a data structure of a DVD according to the firstembodiment of the present invention;

[0120]FIG. 8 is a table showing a correspondence between a framesynchronization code and a frame synchronization signal according to thefirst embodiment of the present invention;

[0121]FIG. 9(a) is a table showing a correspondence of a decoded addressvalue with a frame according to the first embodiment of the presentinvention;

[0122]FIG. 9(b) is a table showing a correspondence of a decoded addressvalue with a sector according to the first embodiment of the presentinvention;

[0123]FIG. 9(c) is a table showing a correspondence of a decoded addressvalue with an ECC block according to the first embodiment of the presentinvention;

[0124]FIG. 10(a) shows a sector structure of a disk that is writtenaccording to a defect management method of skipping only a defectivesector according to a second embodiment of the present invention;

[0125]FIG. 10(b) shows a structure of ECC blocks that is writtenaccording to a defect sector management method of skipping an ECC blockincluding a defective sector according to the second embodiment of thepresent invention; and

[0126]FIG. 11 is a block diagram showing defective sector detectionmeans according to the second embodiment of the present invention.Description of Symbols 101 Optical disk (DVD) 102 Spindle motor 103Optical pickup 104 RF signal processing block 105 Servo block 106 Buffermemory 107 Controller block 108 Control microcomputer 109 Host 111Irradiation light and reflected light 112 Spindle motor control signal113 RF signal 114 Optical pickup control signal 115 Signal between RFsignal processing block and servo block 116 Signal between RF signalprocessing block and controller block 117 Signal between servo block andcontroller block 118 Signal between buffer memory and controller block119 Signal between control microcomputer and controller block 120 Signalbetween host and controller block 121 Signal between controlmicrocomputer and RF signal processing block 122 Signal between controlmicrocomputer and servo block 201 Byte counter 202 Frame synchronizationcounter value address translation decoder 203 Low order ID addresstranslation decoder 204 Adder/subtracter 205 ID high order bit addresstranslation decoder 206 Adder 211 ID information corresponding to datarequested by host 109 212 Positional information on start of storageinto buffer memory 106 213 In-frame address 214 ECC block positionalinformation 215 Buffer memory storage address 301 Channel dataparallelization block 302 Frame synchronization signal generation block303 Data demodulation block 304 Data demodulation block 305 Framesynchronization detection block 306 Sector synchronization interpolationblock 307 Frame synchronization counter block 308 Frame positiondetection block 309 Sector synchronization signal generation block 310Frame position reliability determination block 311 Frame synchronizationcounter value address translation block 321 Channel data 322 Paralleldata 323 Frame synchronization signal 324 Frame synchronization codesignal 325 Sector synchronization signal 326 Sector synchronizationinterpolation signal 327 Absolute frame position signal 328 Frameposition detection result adoption signal 329 Frame position signal 330Frame synchronization code arrangement OK signal 331 Sectorsynchronization signal 332 Frame address 333 Demodulated data 334 Byteclock 401 ID regeneration block 402 ECC block synchronization detectionblock 403 ECC block synchronization interpolation block 404 Sectorsynchronization counter block 405 ID reliability determination block 406ECC block synchronization generation block 407 ID information addresstranslation block 411 ID acquisition signal 412 ECC blocksynchronization detection signal 413 ECC block synchronizationinterpolation signal 414 Absolute sector address signal 415 Addressreliability OK signal 416 High order address determination result signal417 Current ID information signal 418 ECC block synchronization signal419 Sector address 420 ECC block address 501 Frame synchronization codeencoding register A 502 Frame synchronization code encoding register B503 Frame synchronization code position detection decoder 505 Framesynchronization code arrangement OK counter 506 Frame position detectionresult adoption determination circuit 511 (n-1)th frame synchronizationcode signal 512 (n-2)th frame synchronization code signal 513 Frameposition determination condition 521 Frame synchronization codearrangement OK count signal 601 Address comparator A 602 Addresscomparator B 603 Address reliability condition determination decoder 604Selector 605 Incrementer 606 ID retaining register 611 Address componentof ID information of ID acquisition signal 413 612 Error detectionresult component of ID information of ID acquisition signal 413 613Address reliability determination condition 614 Address continuitydetermination signal 618 Address expected value signal 619 Currentaddress selection signal 1101 Physical ID retaining register A 1102Physical ID retaining register B 1103 Incrementer A 1104 Subtracter 1105ID retaining register 1106 Incrementer B 1107 Comparator 1108 Defectivesector detector 1111 ID regeneration signal 1112 Physical ID signal 1113Physical ID acquisition signal 1114 Physical ID signal 1115 Physical IDexpected value signal 1116 Number of defective sectors 1117 ID signal1118 ID expected value signal 1119 ID continuity signal 1120 Defectivesector detection signal

BEST MODE FOR CARRYING OUT THE INVENTION

[0127] As an example of the present invention, an optical diskgeneration device is characterized in that an address used foraccurately storing data read from an optical disk medium into a buffermemory is generated and that even if an abnormality occurs in variouskinds of synchronization indicating a beginning of a data unit due tovarious factors such as a fingerprint or scratch on the optical diskmedium, the address used for accurately storing the data read from theoptical disk medium into the buffer memory can be generated by analyzingthe data read from the optical disk medium and grasping a positionalrelationship between the data read from the optical disk medium and datapreviously stored in the buffer memory.

[0128] As an example of the present invention, an optical disk drive ischaracterized in that means of analyzing the data read from the opticaldisk medium is to analyze the sector identification information readfrom the optical disk medium.

[0129] As an example of the present invention, the optical disk drive ischaracterized in that the means of analyzing the data read from theoptical disk medium is to analyze the frame synchronization code readfrom the optical disk medium.

[0130] As an example of the present invention, the buffer memory addresstranslation device comprises means of reading sector address informationadded to the data read from the optical disk medium, means ofdetermining the reliability of the sector address information read bythe above means, means of interpolating the sector address informationfor a sector the sector address information for which is not determinedto be reliable, means of selecting the information generated by theabove means of reading sector address information or the informationinterpolated by the above means of interpolating the sector addressinformation, and means of generating an address for storage in thebuffer memory based on the above selected information, and canaccurately generate an address for storage of the data read from theoptical disk medium into the buffer memory by generating the address forstorage into the buffer memory using a reliable sector addressinformation even if an abnormality occurs in various kinds ofsynchronization indicating a beginning of a data unit due to variousfactors such as a fingerprint or scratch on the optical disk medium.

[0131] As an example of the present invention, the means of determiningthe reliability of the sector address information of the buffer memoryaddress translation device for sector address information ischaracterized in that it detects an error in the sector addressinformation by using an error detection code added to the sector addressinformation.

[0132] As an example of the present invention, the means of determiningthe reliability of the sector address information of the buffer memoryaddress translation device for sector address information ischaracterized in that it determines continuity of the addressinformation when the current sector address information coincides withthe value of the previous sector address information plus 1.

[0133] As an example of the present invention, the means of selectingthe information generated by the means of reading the sector addressinformation or the information generated by the means of interpolatingthe sector address of the buffer memory address translation device forsector address information is characterized in that it analyzes thecondition of reliability for the sector address information required bythe external control means and the result of reliability determinationfor the sector information to determine the sector address informationto be selected.

[0134] As an example of the present invention, the sector addressinformation reliability determination device comprises means ofdetecting an error of sector address information read from the opticaldisk medium, means of determining the continuity of the sector addressinformation based on the result of the comparison between the currentlyread sector address information and previously read sector addressinformation and the condition set by the external control means, andmeans of determining the continuity of the sector address information incooperation with the means of detecting an error of sector addressinformation with reference to the condition set by the external controlmeans, and, even if there is an error in the sector address informationdue to various factors such as a fingerprint or scratch on the opticaldisk medium, can determine the reliability of the sector addressinformation by checking that the result of the error detection for thesector address information and the continuity of the sector addressinformation satisfy the condition set by the external control means.

[0135] As an example of the present invention, in readout from arewritable optical disk medium storing physical sector addressinformation added to a physical sector besides the sector addressinformation added to data, a defective sector determination devicecomprises means of detecting a position where a difference occursbetween the continuity of the physical sector address information andthe continuity of the sector address information, means of storing thephysical sector address information for which a difference occursbetween the continuity of the physical sector address information andthe continuity of the sector address information, means of detecting thenumber of physical sectors existing between the continuous pieces ofsector address information, and means of informing the external controlmeans of the detection and storage, and can determine the defectivesector by checking the difference between the sector address informationand the physical sector address information even when the defectivesector information is not previously acquired in the optical disk mediumhaving the defective sector information recorded therein.

[0136] As an example of the present invention, the continuity of thephysical sector address information is characterized in that itcomprises means of reading the physical sector address information,means of detecting an error in the physical sector address informationread by the above means, means of storing the previous physical sectoraddress information of the physical sector address information that isdetermined to be reliable by the means of detecting an error in thephysical sector address information, and means of comparing the storedprevious physical sector address information with the current physicalsector address information, and determines the continuity of thephysical sector address that is determined to be reliable by the meansof detecting an error in the physical sector address information.

[0137] As an example of the present invention, the continuity of thesector address information is characterized in that it comprises meansof reading the sector address information, means of detecting an errorin the sector address information read by the above means, means ofstoring the previous sector address information of the sector addressinformation that is determined to be reliable by the means of detectingan error in the sector address information, and means of comparing thestored previous sector address information with the current sectoraddress information, and determines the continuity of the sector addressthat is determined to be reliable by the means of detecting an error inthe sector address information.

[0138] As an example of the present invention, the means of detecting aposition where a difference occurs between the continuity of thephysical sector address information and the continuity of the sectoraddress information is characterized in that it detects that there are aplurality of physical sectors for which the physical sector addressinformation is determined to be continuous between two continuoussectors for which the sector address information is determined to becontinuous, and detects the physical sector having no user data recordedtherein.

[0139] As an example of the present invention, the means of storing thephysical sector address information for which a difference occursbetween the continuity of the physical sector address information andthe continuity of the sector address information is characterized inthat it stores the physical sector address information of the physicalsector for which the sector address information of the present inventionis not continuous.

[0140] As an example of the present invention, the means of detectingthe number of physical sectors existing between the continues pieces ofsector address information is characterized in that it recognizes thenumber of physical sectors for which the physical sector addressinformation is determined to be continuous and that exist between thetwo continuous sectors for which the sector address information isdetermined to be continuous.

[0141] As an example of the present invention, the ECC blocksynchronization detection device comprises means of detecting an errorof sector address information that is read from an optical disk mediumin which an error correcting code is added thereto across n sectors(n=integer) and the error correcting code is accommodated in thecontinuous n sectors, means of, if the error detection means detects noerror in the sector address information, finding the quotient of “(theread sector address information)/(the number of sectors constituting anECC block)”, means of storing the quotient of the sector addressinformation found by the above means, and means of, if the means ofdetecting an error of sector address information detects no error in thecurrent sector address information, comparing the quotient of the sectoraddress information stored in the above means with the current quotientand determining that the ECC block synchronization is detected if thecomparison does not result in a match, and even if the ECC blocksynchronization is lost by various factors such as fingerprint orscratch on the optical disk medium, loss of data can be reduced by usingthe quotient of “(the read sector address information)/(the number ofsectors constituting an ECC block)” to detect the ECC blocksynchronization.

[0142] As an example of the present invention, the buffer memory addresstranslation device comprises means of reading a frame synchronizationcode added to data read from the optical disk medium, storage means ofencoding the frame synchronization codes read by the above means andsequentially storing the same, the number of codes stored in the storagemeans being capable of being set by an external control means, means ofdigitizing a frame position based on the arrangement of the codes storedin the storage means, means of determining whether the values obtainedby digitizing the frame positions by the above means are continuous,means of counting the number of the frame positions determined to becontinuous by the above means, means of comparing the number of thecontinuous frame positions counted by the above means with a thresholdthat can be set by the external control means and if the comparisonresult satisfies a condition, determining that the value obtained bydigitizing the frame position by the above means to be the frameposition, and if the comparison result does not satisfy the condition,performing interpolation based on a previous frame position for whichthe condition is satisfied and regarding the interpolated frame positionas the frame position, and means of generating an address for storageinto the buffer memory according to the frame position determined by theabove means, and even if the frame synchronization is lost by variousfactors such as a fingerprint or scratch on the optical disk medium,loss of data can be reduced by using the frame synchronization code torecognize the frame position of the data read from the disk.

[0143] Embodiments of the present invention will be described below withreference to the drawings.

[0144] (First Embodiment)

[0145] First, a first embodiment will be described with reference toFIGS. 1, 2, 3, 4, 5, 6, 7, 8, 9, and 10.

[0146]FIG. 1 shows a structure of an optical disk drive 1201 of thisembodiment.

[0147] In FIG. 1, reference numeral 101 denotes an optical disk mediumhaving information recorded therein, reference numeral 102 denotes aspindle motor for rotating the optical disk medium, reference numeral103 denotes an optical pickup that irradiates the optical disk mediumwith laser light and converts the intensity of the light reflectedtherefrom into voltage, reference numeral 104 denotes an RF signalprocessing block that converts the signal converted into voltage by theoptical pickup 103 into a binary signal and generates a clocksynchronized with the binary signal, reference numeral 105 denotes aservo block for controlling the rotation of the spindle motor 102 andposition of the optical pickup 103, reference numeral 106 denotes abuffer memory for retaining various kinds of information, referencenumeral 107 denotes a controller block for carrying out storage of thebinary signal generated in the RF signal processing block 104 into thestorage medium (hereinafter referred to as buffer memory) 106, errorcorrection processing thereof, data transfer to/from a host 109,interpretation of an instruction from a control microcomputer 108 or thelike, reference numeral 108 denotes the control microcomputer forcontrolling the RF signal processing block 104, servo block 105, andcontroller block 107, and reference numeral 109 denotes a host thatissues a replay request for data of the optical disk medium 101 or thelike. These components 102, 103, 104, 105, 106, 107, and 108 constitutethe optical disk drive, and constitute means capable of servicing areplay request of the optical disk medium 101 issued by the host 109.

[0148] Now, an operation of the optical disk drive when the replayrequest of the optical disk medium 101 is issued by the host 109 will bedescribed.

[0149] First, the host 109 requests a position and quantity of data tobe replayed of the optical disk medium 101 from the controller block107. Upon receiving the request from the host 109, the controller block107 informs the control microcomputer 108 of the details of the requestfrom the host 109. The control microcomputer 108 analyzes the requestfrom the host 109, issues to the servo block 105 an instruction forcontrolling the rotation of the optical disk medium 101 and moving theoptical pickup 103 to the vicinity of a position where the data the host109 requests for the replay thereof is recorded, and instructs thecontroller block 107 to transfer the data the host 109 requests for thereplay thereof to the host 109.

[0150] Upon receiving the instruction from the control microcomputer108, the servo block 105 follows the instruction to allow the spindlemotor 102 to be rotated at a predetermined speed and the optical pickup103 to be moved.

[0151] The optical disk medium 101 is rotated by the spindle motor 102.The optical disk medium 101 has information recorded therein by havingpits formed in tracks thereof.

[0152] The optical pickup 103 moved by the servo block 105 irradiatesthe rotating optical disk medium 101 with light and receives the lightreflected by the optical disk medium 101. In this regard, the lightreflected by the optical disk medium 101 varies in intensity under theinfluence of the pits formed on the optical disk medium 101. Uponreceiving the reflected light, the optical pickup 103 outputs an RFsignal 113 obtained by converting the intensity of the reflected lightinto voltage to the RF signal processing block 104 and outputsinformation on the shape and position of the reflected light to theservo block 105.

[0153] Upon receiving the information on the shape and position of thereflected light, the servoblock 105 detects a focal point of the lightapplied to the optical disk medium 101 and a track position where thedata is recorded of the optical disk medium 101, and moves the opticalpickup 103 vertically and horizontally to adjust the position thereof toa position where data can be read from the optical disk medium 101.

[0154] Upon receiving the RF signal 113 from the optical pickup 103, theRF signal processing block 104 converts the signal into a binary signal,generates a clock synchronized with the binary signal, and outputs it tothe controller block 107. Hereinafter, the binary signal is referred toas channel data, and the clock synchronized with the binary signal isreferred to as a channel clock.

[0155] Upon receiving the channel data and channel clock from the RFsignal processing block 104, the controller block 107 samples thechannel data on the channel clock, converts the channel data into apredetermined format, and acquires address information from theconverted data. Upon acquiring the address information, the controllerblock 107 provides the acquired address information for the controlmicrocomputer 108, and follows the instruction from the controllermicrocomputer to store the data converted into the predetermined formatinto the buffer memory 106. Furthermore, the controller block 107performs the error correction processing and error detection processingon the data stored in the buffer memory 106, informs the controlmicrocomputer 108 of the results, and follows the instruction from thecontrol microcomputer 108 to transfer the data stored in the buffermemory 106 to the host 109.

[0156] Upon receiving the address information and the results of theerror correction processing and error detection processing from thecontroller block 107, the control microcomputer 108 analyzes thereceived information and instructs the servo block 105 and controllerblock 107 to repeat the above process a certain number of times untilthe controller block 107 transfers the data requested by the host 109 tothe host 109. In the case where the data cannot be transferred to thehost even though the above process has been repeated the certain numberof times, the control microcomputer 108 notifies the host 109 via thecontroller block 107 of the reason why the requested data cannot betransferred.

[0157] Next, for the case where the optical disk medium 101 is a DVD, anoperation of the controller block 107 converting the channel datareceived from the RF signal processing block 104 into a structure shownin FIG. 7 to store it into the buffer memory 106 will be described. Inthe following description, the optical disk medium 101 is referred to asDVD 101.

[0158]FIG. 7 shows a data structure of the DVD 101, a constituent unitof the DVD 101 being a frame, a sector, or an ECC block. A frame isconstituted by two bytes of frame synchronization and a framesynchronization code and the following 91 bytes of data. The framesynchronization code includes eight kinds of codes, that is, SY0 to SY7,arranged as shown in FIG. 7. A sector is constituted by 26 framesbeginning with a frame having the code SY0. At the beginning of theframe having the code SY0, that is, at the beginning of the sector,there is a region having disk information and address information of thesector, referred to as ID, stored therein. An ECC block is constitutedby 16 sectors beginning with a sector with the low order four bits ofthe ID being “0000b”. The ID information is represented in thehexadecimal notation, and when the sector is advanced by one, theaddress information of the sector included in ID is advanced by one.Accordingly, the low order four bits of the ID of the leading sector ofany ECC block is always “0000b”.

[0159] The channel data input to the controller block 107 from the RFsignal processing block 104 is first subject to a demodulationprocessing in the structure shown in FIG. 3. That is, FIG. 3 shows astructure of demodulation processing means of this embodiment. In FIG.3, reference numeral 301 denotes a channel data parallelization block,reference numeral 302 denotes a frame synchronization generation block,reference numeral 303 denotes a frame synchronization code encodingblock, reference numeral 304 denotes a data demodulation block,reference numeral 305 denotes a sector synchronization detection block,reference numeral 306 denotes a sector synchronization interpolationblock, reference numeral 307 denotes a frame synchronization counterblock, reference numeral 308 denotes a frame position detection block,reference numeral 309 denotes a sector synchronization signal generationblock, reference numeral 310 denotes a frame synchronization positionreliability determination block, and reference numeral 311 denotes aframe synchronization counter value address translation block.

[0160] The channel data 321 received from the RF signal processing block104 is taken in the channel data parallelization block 301, which is ashift register, at every channel clock, and the output of the shiftregister is output to the frame synchronization signal generation block302, frame synchronization code encoding block 303, and datademodulation block 304 as parallel data 322.

[0161] Upon receiving the parallel data 322, the frame synchronizationsignal generation block 302 detects the frame synchronization includedin the parallel data 322 each time the channel data 321 is input. Afterdetecting the frame synchronization, the frame synchronization signalgeneration block 302 counts pieces of the input channel data 321 withreference to the detected frame synchronization, removes a framesynchronization if the frame synchronization is detected at a pointother than the vicinity of a point where the next frame synchronizationis expected to be detected, interpolates a frame synchronizationaccording to the number of pieces of the input channel data if any framesynchronization is not detected in the vicinity of a point where thenext frame synchronization is expected to be detected, and outputs thedetected frame synchronization or interpolated frame synchronization tothe frame synchronization code encoding block 303, data demodulationblock 304, sector synchronization detection block 305, sectorsynchronization interpolation block 306, frame synchronization counterblock 307, and frame position detection block 308 as a framesynchronization signal 323.

[0162] Upon receiving the parallel data 322 and frame synchronizationsignal 323, the frame synchronization code encoding block 303 extracts a14-bit frame synchronization code added to the frame synchronizationfrom the parallel data 322 when receiving the frame synchronizationsignal 323, and generates a frame synchronization code signal 324representing each of the eight frame synchronization codes SY0 to SY7 by8 bits as shown in FIG. 8. The generated frame synchronization codesignal 324 is output to the sector synchronization detection block 305and frame position detection block 308.

[0163] Upon receiving the parallel data 322 and frame synchronizationsignal 323, the data demodulation block 304 generates demodulated data333 from the parallel data 322 with reference to the framesynchronization signal 302, and generates a byte clock 334 each time thedemodulated data is generated. The byte clock 334 serves as a timing ofthe reception of the demodulated data 333 or is used for counting thenumber of pieces of the demodulated data.

[0164] Upon receiving the frame synchronization signal 323 and framesynchronization code signal 324, the sector synchronization detectionblock 305 compares the frame synchronization code signal 324 with“00000001b” for each of the frame synchronization signal, and if theycoincide with each other, it is determined that a sector synchronizationis detected. When it is determined that the sector synchronization isrecognized, the sector synchronization detection block 305 generates asector synchronization signal 325 and outputs it to the sectorsynchronization signal generation block 309.

[0165] Upon receiving the frame synchronization signal 323 and framesynchronization code signal 324, the frame position detection block 308outputs a frame position signal 329 indicating the ordinal position ofthe frame in the sector to the frame synchronization counter block 307,and if the frame position can be detected from the frame synchronizationcode signal 324, outputs a frame synchronization code arrangement OKsignal 330 to the frame position reliability determination block 310.

[0166] The frame position reliability determination block 310 monitorsthe frame synchronization code arrangement OK signal 330, and if theframe position detected from the frame synchronization code arrangementOK signal 330 is determined to be reliable, outputs a frame positiondetection result adoption signal 328 to the frame synchronizationcounter block 307.

[0167] Now, an operation of the frame position detection block 308 andframe position reliability determination block 310 will be described indetail with reference to FIG. 5. In FIG. 5, reference numeral 501denotes a frame synchronization code encoding register A, referencenumeral 502 denotes a frame synchronization code encoding register B,reference numeral 503 denotes a frame synchronization code positiondetection decoder, reference numeral 505 denotes a frame synchronizationcode arrangement OK counter, and reference numeral 506 denotes a frameposition detection result adoption determination circuit. Here, theframe position detection block 308 is constituted by the framesynchronization code encoding register A 501, frame synchronization codeencoding register B 502, and frame position detection decoder 503, andthe frame position reliability determination block 310 is constituted bythe frame synchronization code arrangement OK counter 505 and frameposition detection result adoption determination circuit 506.

[0168] Upon receiving the frame synchronization signal 323 and framesynchronization code signal 324, the frame position detection block 308outputs a value of the frame synchronization code encoding register A501 as a (n-1)th frame synchronization code signal 511 and a value ofthe frame synchronization code encoding register B 502 as a (n-2)thframe synchronization code signal 512 to the frame position detectiondecoder 503 for each frame synchronization signal 323.

[0169] Besides, for each frame synchronization signal 323, the value ofthe frame synchronization code encoding register A 501 is stored in theframe synchronization code encoding register B 502, and the framesynchronization code signal 324 is stored in the frame synchronizationcode encoding register A 501.

[0170] In this regard, the frame synchronization code encoding registerA 501 and frame synchronization code encoding register B 502 areconfigured as a shift register.

[0171] The frame synchronization position decoder 503 takes in valuesincluded in the frame synchronization code 324, (n-1)th framesynchronization code signal 511, and (n-2)th frame synchronization codesignal 512 for each frame synchronization signal 323. Here, the threevalues taken in the frame position detection decoder 503 constitute theframe synchronization codes of a current frame, frame one frame ahead ofthe current frame, and frame two frames ahead of the current frame.

[0172] The frame position detection decoder 503 having the values of thethree frame synchronization codes taken therein checks them against thearrangement of the frame synchronization codes shown in FIG. 7, outputsthe ordinal number of the frame in the sector to the framesynchronization counter block 307 as the frame position signal 329, andif there is a matched arrangement as a result of the check against theframe synchronization code arrangement, outputs the framesynchronization code arrangement OK signal 330 to the frame positionreliability determination block 310.

[0173] Upon receiving the frame synchronization code arrangement OKsignal 330, the frame position reliability determination block310monitors the frame synchronization code arrangement OK signal 330 foreach frame synchronization signal 323 in the frame synchronization codearrangement OK counter 505. The frame synchronization code arrangementOK counter 505 is such a type of counter that increments the count valueif there is a frame synchronization code arrangement OK signal 330, andclears the count value if there is no frame synchronization codearrangement OK signal 330, which outputs the count value as anarrangement OK count signal 521 to the frame position detection resultadoption determination circuit 506.

[0174] Upon receiving the frame synchronization code arrangement OKcount signal 521, the frame position detection result adoptiondetermination circuit 506 compares a frame position determinationcondition 513 preset by the control microcomputer 108 with the framesynchronization code arrangement OK count signal 521, and if the framesynchronization code arrangement OK count signal 521 is larger than theframe position determination condition, outputs a frame positiondetection result adoption signal 328 to the frame synchronizationcounter block 307.

[0175] Provided that the frame position determination condition 513 is5, for example, the frame position detection result adoptiondetermination circuit 506 outputs the frame position detection resultadoption signal 328 to the frame synchronization counter block 307 whenthe frame synchronization code arrangement OK count signal 521 is 6 ormore.

[0176] Thus, the frame position detection result adoption signal 328 isoutput if the number of the continuously detected frame positions islarger than the number of times specified by the frame positiondetermination condition 513. In other words, if the frame positions aresuccessfully continuously detected, the frame position reliabilitydetermination block 310 determines the detected frame positions to bereliable and outputs the frame position detection result adoption signal328, and if the frame positions are not successfully continuouslydetected, the frame position reliability determination block 310determines the detected frame positions to be unreliable and does notoutput the frame position detection result adoption signal 328.

[0177] So far, the frame position detection block 308 and frame positionreliability determination block 310 have been described in detail.

[0178] Referring to FIG. 3 again, the frame synchronization counterblock 307 is such a type of counter that counts the number of frames inthe sector by clearing the count value when receiving the sectorsynchronization signal 331 output from the sector synchronization signalgeneration block 309 and incrementing the count value when receiving theframe synchronization signal 323.

[0179] In addition, the frame synchronization counter block 307 has acorrection function of integrating the frame position signal 329received from the frame position detection block 308 into the countervalue when the frame position detection result adoption signal 328received from the frame position reliability determination block 310 isvalid.

[0180] Therefore, even if the counter value representing the number offrames in the sector becomes inaccurate due to an abnormality occurringin the frame synchronization signal 323 or the like, the above-describedcorrection function allows the counter value to recover to a normalvalue.

[0181] The count value of the frame synchronization counter block 307 isoutput to the sector synchronization interpolation block 306 and framesynchronization counter value address translation block 311 as anabsolute frame position signal 326.

[0182] The absolute frame position signal 327 is a signal that indicatesthe position of a frame in a sector, which assumes one of 26 values from0 to 25. Furthermore, the absolute frame position signal 327 isassociated with the frame position in the sector in such a manner thatthe value 0 corresponds to the first frame, the value 1 corresponds tothe second frame, and the value 25 corresponds to the 26th frame.

[0183] The sector synchronization interpolation block 306 monitors theabsolute frame position signal 327 for each frame synchronization signal323, and when the absolute frame position signal 327 indicates that thecurrent frame is the 26th frame, determines that the next framesynchronization becomes the beginning of a sector.

[0184] Upon determining that the next frame synchronization representsthe beginning of a sector, the sector synchronization interpolationblock 306 generates a sector synchronization interpolation signal 326when receiving the next frame synchronization signal 323, and outputs itto the sector synchronization signal generation block 309.

[0185] The sector synchronization signal generation block 309 generatesthe sector synchronization signal 331 by selecting the sectorsynchronization detection signal 325 and sector synchronizationinterpolation signal 326 according to the instruction from the controlmicrocomputer 108, and outputs it to the frame synchronization counterblock 307 and a block for controlling the ECC block synchronizationdescribed below.

[0186] That is, the sector synchronization signal generation block 309selects the sector synchronization detection signal 325 or sectorsynchronization interpolation signal 326 that is more reliable togenerate the sector synchronization signal 331. For example, if thesector synchronization detection signal 325 is not reliable, the sectorsynchronization interpolation signal 326 is selected. Accordingly, sincethe sector synchronization interpolation signal 326 is selected if anyomission or error occurs in detection of the sector synchronizationdetection signal 325 in the sector synchronization detection block 305,a reliable sector synchronization signal 331 can be output.

[0187] The frame synchronization counter value address translation block331 decodes the absolute frame synchronization position signal 327 andgenerates a frame address 332 that is a base address of the buffermemory for storing the frame.

[0188] Next, an ECC block synchronization processing following theabove-described frame synchronization processing and sectorsynchronization processing will be described with reference to FIG. 4.That is, FIG. 4 shows a structure of ECC block processing means 1204 ofthis embodiment. In FIG. 4, reference numeral 401 denotes an IDregeneration block, reference numeral 402 denotes an ECC blocksynchronization detection block, reference numeral 403 denotes an ECCblock synchronization interpolation block, reference numeral 404 denotesa sector synchronization counter block, reference numeral 405 denotes anID reliability determination block, reference numeral 406 denotes an ECCblock synchronization signal generation block, and reference numeral 407denotes an ID information address translation block.

[0189] First, the ID regeneration block 401 receives the demodulateddata 333 and byte clock 334 from the data demodulation block 304, andthe sector synchronization signal 331 from the sector synchronizationsignal generation block 309, and immediately after receiving the sectorsynchronization signal 331, acquires 4-byte ID information and a 2-byteEDC parity of the ID information from the demodulated data 333 at thetiming of the byte clock 334. Upon receiving the ID information and EDCparity of the ID information, the ID regeneration block 401 performserror detection on the acquired ID information and outputs 24 bits ofthe address component of the ID information and 1 bit of the errordetection result component of the ID information as an ID acquisitionsignal 411 to the ECC block synchronization detection block 402, sectorsynchronization counter block 404, and ID reliability determinationblock 405.

[0190] The ECC block synchronization detection block 402 receives the IDacquisition signal 411 for each sector synchronization signal 331, andif the error detection result component of the ID information of the IDacquisition signal 411 indicates that the acquired ID information iscorrect, compares the low order four bits of the address component ofthe ID information of the ID acquisition signal 411 with “0000b”. If thecomparison results in a match, or a high order address determinationresult signal 416 described later that is generated in the IDreliability determination block 405 is input thereto, the ECC blocksynchronization detection block 402 generates an ECC blocksynchronization detection signal 412 and outputs it to the ECC blocksynchronization signal generation block 406.

[0191] Upon receiving the sector synchronization signal 331, IDacquisition signal 411, and ECC block synchronization signal 418described later, the ID reliability determination block 405 determineswhether the ID acquisition signal 411 is reliable or not, and outputs anaddress reliability OK signal 415 to the sector synchronization counterblock 404 if the ID acquisition signal 411 is determined to be reliable.In addition, if the ID reliability determination block 405 detects achange of the ECC block, it outputs the high order address determinationresult signal 416 to the ECC block synchronization detection block.Furthermore, the ID reliability determination block 405 improves thereliability of the ID acquisition signal 411 and outputs it as an IDinformation signal 417 to the ID information address translation block407.

[0192] Now, an operation of the ID reliability determination block 405will be described with reference to FIG. 6. In FIG. 6, reference numeral601 denotes an address comparator A, reference numeral 602 denotes anaddress comparator B, reference numeral 603 denotes an addressreliability condition determination decoder, reference numeral 604denotes a selector, reference numeral 605 denotes an incrementer, andreference numeral 606 denotes an ID retaining register.

[0193] If an error detection result component 612 of the ID informationof the ID acquisition signal 411 indicates that the acquired ID iscorrect, upon receiving the ID acquisition signal 411, the IDreliability determination block 405 compares an address component 611 ofthe ID information of the ID acquisition signal 411 with an addressexpected value signal 618 described later in the address comparator A601 to determine the continuity of address. Since the address expectedvalue signal 618 indicates the ID acquisition signal 411 to be inputsubsequently, coincidence between the two signals indicates thecontinuity of address. The address continuity determination result isoutput as an address continuity determination signal 614 to the addressreliability condition determination decoder 603.

[0194] The address comparator B 602 compares the high order 20 bits ofthe address component 611 of the ID information of the ID acquisitionsignal 411 with the high order 20 bits of the address component of acurrent ID information signal417 described later, and outputs a highorder address determination result signal 416 to the ECC blocksynchronization determination block 402 if the comparison does notresult in a match. Here, the address component 611 of the ID informationof the ID acquisition signal 411 and address component of the current IDinformation signal 417 described later are two continuous addresses atthe timing of the sector synchronization signal 331. In addition, theECC block of the DVD 101 is constituted by 16 sectors each beginningwith the low order four bits of the address represented in thehexadecimal notation included in the ID information of “0000b”.Therefore, the high order address determination result signal 416 can beconsidered to indicate the comparison result of quotients of (readsector address information)/(number of sectors constituting the ECCblock)” of the two continuous sectors, and indicate the change of theECC block.

[0195] The address reliability condition determination decoder 603,according to the address reliability determination condition 613 presetby the control microcomputer 108, decodes the error detection resultcomponent 612 of the ID information of the ID acquisition signal 411 andthe address continuity determination signal 614, and generates theaddress reliability OK signal 415 if the address reliabilitydetermination condition 613 is satisfied. The address reliability OKsignal 415 is output to the selector 604 and sector synchronizationcounter block 404.

[0196] The selector 604 selects the ID acquisition signal 411 if theaddress reliability OK signal 415 indicates that the ID acquisitionsignal 411 is reliable, or selects the address expected value signal 616described later if the address reliability OK signal 415 indicates thatthe ID acquisition signal 411 is not reliable, and outputs the selectedaddress information as a current address selection signal 615 to the IDretaining register 606.

[0197] The ID retaining register 606 stores the current addressselection signal 619 for each sector synchronization signal 331, andoutputs the stored value as the current ID information signal 417 to theincrementer 605 and ID information address translation block 407.

[0198] The incrementer 605 is a circuit that adds 1 to the value of thecurrent ID information signal 417, and outputs the addition result asthe address expected value signal 616 to the selector 604 and addresscomparator A 601. The reason why the addition result becomes the addressexpected value signal 616 is that the address component included in theID information of the DVD 101 has a rule that when the sector isadvanced by one, the address component is also advanced by one.

[0199] So far, the operation of the ID reliability determination block405 has been described in detail.

[0200] Referring to FIG. 4 again, upon receiving the sectorsynchronization signal 331, ID information acquisition signal 411,address reliability OK signal 415, and ECC block synchronization signal418 described later, the sector synchronization counter block 404operates at each sector synchronization signal 331 to take in the loworder four bits of the address component of the ID acquisition signal411 as the counter value if the address reliability OK signal 415indicates that the ID acquisition signal 411 is reliable, or incrementsthe counter value if the address reliability OK signal 415 indicatesthat the ID acquisition signal 411 is not reliable, and is cleared bythe ECC block synchronization signal 418. Therefore, if the IDinformation is determined to be reliable, the sector synchronizationcounter block 404 has its counter value corrected by the ID information.The counter value is output as an absolute sector address signal 414 tothe ECC block synchronization interpolation block 403.

[0201] The ECC block synchronization interpolation block 403 monitorsthe absolute sector address signal 414 for each sector synchronizationsignal 331, and generates the ECC block synchronization interpolationsignal 413 at the timing of the sector synchronization signal 331 whenthe absolute sector address signal 414 indicates 15, that is, the lastsector in the ECC block.

[0202] The ECC block synchronization signal generation block 406 selectsthe ECC block synchronization detection signal 412 and ECC blocksynchronization interpolation signal 413 according to the conditionpreset by the control microcomputer, and generates the ECC blocksynchronization signal 418. The ECC block synchronization signal 418 isoutput to the sector synchronization counter block 404 and IDinformation address translation block 407.

[0203] The ID information address translation block 407 takes in thecurrent ID information signal 418 at each ECC block synchronizationsignal 419 and generates a sector address 419 and ECC block address 420that are the base addresses of the buffer memories storing the sectorand ECC block, respectively. Here, the sector address 419 must be set toinclude 26 or more regions for storing the frames, and the ECC blockaddress 420 must be set to include 16 or more regions for storing thesectors.

[0204] Lastly, an eventual generation of a data storage address in thebuffer memory 106 will be described with reference to FIG. 2. FIG. 2shows a structure of address generation means 1202 of this embodiment.In FIG. 2, reference numeral 201 denotes a byte counter, referencenumeral 202 denotes a frame synchronization counter value addresstranslation decoder, reference numeral 203 denotes a low order IDaddress translation decoder, reference numeral 204 denotes anadder/subtracter, reference numeral 205 denotes a high order ID addresstranslation decoder, and reference numeral 206 denotes an adder. In thisregard, the frame synchronization counter value address translationblock 311 in FIG. 3 is equivalent to the frame synchronization countervalue address translation decoder 202 in FIG. 2, and the ID informationaddress translation block 407 in FIG. 4 is constituted by the low orderID address translation decoder 203, adder/subtracter 204, and high orderID address translation decoder 204.

[0205] The byte counter 201 is a counter that is cleared by the framesynchronization signal 323 and counts the byte clock 334. That is, thebyte counter 201 is cleared at the beginning of a frame and counts thenumber of the demodulated pieces of data, and the counter value thereofbecomes the address of the buffer memory 106 for storing the 91 bytes inthe frame as it is. The counter value of the byte counter 201 is outputas an in-frame address 213 to the adder 205.

[0206] The frame synchronization counter value address translationdecoder 202 is a decoder that takes in the absolute frame positionsignal 327 at the frame synchronization signal 323 and provides anoutput shown in FIG. 9(a) with respect to the input of the absoluteframe position signal 327, and the decoding result is output as theframe address 332 to the adder 205.

[0207] The low order ID address translation decoder 203 is a decoderthat takes in the low order four bits of the current ID informationsignal 417 at the sector synchronization signal 331 and provides anoutput shown in FIG. 9(b) with respect to the input of the low orderfour bits of the current ID information signal 417, and the decodingresult is output as the sector address 419 to the adder 205.

[0208] The adder/subtracter 204 subtracts the high order 20 bits of theID information 221 corresponding to the data that is preset by thecontrol microcomputer 108 and requested from the host 109 from the highorder 20 bits of the current ID information signal 417. In this process,the respective low order four bits thereof are rounded down. Positionalinformation 212 on a start of storage into the buffer memory 106 isadded to the calculation result, and the result thereof is output as ECCblock position information 214 to the high order ID address translationdecoder 204.

[0209] The high order ID address translation decoder 204 is a decoderthat takes in the ECC block position information 214 for each ECC blocksynchronization signal 418 and provides an output shown in FIG. 9(c)when the remainder of the division (ECC block position information214)/(number of the ECC blocks capable of being stored in the buffermemory 106) is input thereto as the absolute ECC block address, and thedecoding result is output as an ECC block address 223 to the adder 205.Here, in the example shown in FIG. 9(c), the number of the ECC blockscapable of being stored in the buffer memory 106 is 4.

[0210] The adder 205 is an adder that adds the in-frame address 213,frame address 332, sector address 419, and ECC block address 420together, and the result of the addition becomes a buffer memory storageaddress 215.

[0211] With such a configuration, in the case where the framesynchronization cannot be detected or is detected excessively, when theframe synchronization begins to be normally detected, the frame positiondetection block 308 detects a frame position, and the frame positionreliability determination block 310 determines whether the detectedframe position is reliable or not. Accordingly, a highly accurate framesynchronization position can be loaded into the frame synchronizationcounter block 307, and an absolute frame position in a sector stored inthe buffer memory 106 can be properly corrected by the framesynchronization counter value address translation decoder 202.

[0212] In addition, in the case where the sector synchronization cannotbe detected or is detected excessively, when the sector synchronizationbegins to be normally detected, highly reliable ID information can beacquired in the ID reliability determination block 405, and an absolutesector position in an ECC block stored in the buffer memory 106 and anabsolute ECC block position in the buffer memory 106 can be properlycorrected by inputting the ID information into the low order ID addresstranslation decoder 203 and high order ID address translation decoder204.

[0213] Furthermore, in replay of a disk having data written thereonaccording to a defect sector management method for a DVD-RAM of skippingonly a defective sector as shown in FIG. 10(a) or a disk having datawritten thereon according to a defect sector management method for aDVD-RAM of skipping an ECC block including a defective sector as shownin FIG. 10(b), even if positional information of a defective sector isnot provided so that data of the defective sector is stored in thebuffer memory 106, the addresses of the ID information before and afterthe defective sector are consecutive and a highly reliable IDinformation can be acquired in the ID reliability determination block405, and therefore, the region of the buffer memory 106 storing the dataof the defective sector can be overwritten with correct data so that thedisk including the defective sector can be replayed without thedefective sector being noticed.

[0214] As described above, even if the data read from the DVD 101 cannotbe stored in the buffer memory 106, the address of the data storage intothe buffer memory 106 is corrected to be normal by detecting an absoluteposition of the data in each of the data structures by means of theframe position detection block 308, frame position reliabilitydetermination block 310, and ID reliability determination block 405, andtranslating it into an address by means of the frame synchronizationcounter value address translation decoder 202, low order ID addresstranslation decoder 203, and high order ID address translation decoder204, and accordingly, an optical disk drive with an enhanced replayingcapability can be constructed.

[0215] (Second Embodiment)

[0216] Next, a second embodiment will be described with reference toFIG. 11. FIG. 11 shows a structure of defective sector detection means1205 of this embodiment. The same components as those in the previousembodiment are given the same reference numerals, and descriptionthereof is omitted.

[0217] In FIG. 11, reference numeral 1101 denotes a physical IDretaining register A, reference numeral 1102 denotes a physical IDretaining register B, reference numeral 1103 denotes an incrementer A,reference numeral 1104 denotes a subtracter, reference numeral 1105denotes an ID retaining register, reference numeral 1106 denotes anincrementer B, reference numeral 1107 denotes a comparator, andreference numeral 1108 denotes a defective sector detector.

[0218] The physical ID retaining register A 1101 monitors an errordetection component of the ID information of an ID regeneration signal1111 for each physical ID signal 1112, and if it is indicated that theacquired physical ID is free of error, takes in an address component ofthe ID information of the ID regeneration signal 1111, and outputs it asa physical ID acquisition signal 1113 to the physical ID retainingregister B 1102 and subtracter 1104. Here, the physical ID signal 1112becomes capable of being generated by configuring the framesynchronization generation signal block 302 so as to detect not only theframe synchronization but also an AM that is a synchronization of thephysical ID, and supplying the physical ID signal 1112 to the datademodulation block 304 allows the physical ID to be generated in the IDregeneration block 401. Therefore, the ID regeneration signal 1111 isequivalent to the output of the ID regeneration block 401. In thisregard, the AM is described in the DVD-RAM format and is followed by thedescription of the physical ID.

[0219] The physical ID retaining register B 1102 and ID retainingregister 1105 monitor the error detection component of the IDinformation of the ID regeneration signal 1111 for each sectorsynchronization signal 331. If it is indicated that the acquired ID isfree of error, the physical ID retaining register B 1102 takes in thephysical ID retaining register A 1101 and outputs it as a physical IDsignal 1114 to the incrementer A 1103, and the ID retaining register1105 takes in the address component of the ID information of the IDregeneration signal 1111 and outputs it as an ID signal 1117 to theincrementer B 1106.

[0220] That is, even if the sector synchronization signal 331 is input,when it is indicated that the ID acquired by the ID regeneration signal1111 has an error, the physical ID retaining register A 1101 is nottaken in the physical ID retaining register B 1102, and the physical IDsignal 1114 is not output to the incrementer A 1103. Furthermore, theaddress component of the ID information of the ID regeneration signal1111 is not taken in the ID retaining register 1105, and the ID signal1117 is not output to the incrementer B 1106.

[0221] As a result, the physical ID retaining register B 1102 storestherein only the physical ID that is reliably free of error, and onlythe physical ID signal 114 of the physical ID that is reliably free oferror is output to the incrementer A1103. In addition, the ID retainingregister 1105 stores therein only the address component of the IDinformation that is reliably free of error, and only the ID signal 1117that is reliably free of error is output to the incrementer B 1106.

[0222] The incrementer A 1103 increments the physical ID signal 1114 by1, and outputs the result as a physical ID expected value signal 1115 tothe subtracter 1104.

[0223] The incrementer B 1106 increments the ID signal 1117 by 1, andoutputs the result as an ID expected value signal 1118 to the comparator1107.

[0224] The subtracter 1104 subtracts the physical ID expected value 1115from the physical ID acquisition signal 1113 to generate the number ofdefective sectors 1116. The number of defective sectors 1116 is outputto the defective sector detector 1108.

[0225] If the error detection component of the ID information of the IDinformation signal 1111 indicates that the acquired ID information iscorrect, the comparator 1107 compares the address component of the IDinformation of the ID information signal 1111 with the ID expected valuesignal 1118, and if there is a match between the two signals, outputs anID continuity signal 1119 to the defective sector detector.

[0226] In the case where the defective sector detector 1108 receives theID continuity signal 1119 and the number of defective sectors 1116 isnot zero, the defective sector detector determines that a defectivesector is detected and outputs a defective sector detection signal 1120.If the defective sector detection signal 1120 is output, the valueindicated by the number of defective sectors 1116 becomes valid. Inaddition, the physical ID expected signal 1115 indicates the beginningof the defective sector.

[0227] That is, if the address components of the reliable two pieces ofID information are continuous and the two physical IDs are notcontinuous, there is a defective sector between the sectors associatedwith the above-described two pieces of ID information. In this way, thedefective sector detector 1108 detects a defective sector.

[0228] With such a configuration, in replay of a disk having datawritten thereon according to a defect sector management method for aDVD-RAM of skipping only a defective sector as shown in FIG. 10(a) or adisk having data written thereon according to a defect sector managementmethod for a DVD-RAM of skipping an ECC block including a defectivesector as shown in FIG. 10(b), the presence of a defective sector, thestart address of the defective sector, and the number of defectivesectors can be detected when the condition that the subtracter 114 doesnot exhibit zero is satisfied and the comparator 1107 indicates thecontinuity of the ID information.

[0229] In this way, since the presence of a defective sector, the startaddress of the defective sector, and the number of defective sectors canbe detected when the condition that the subtracter 1104 does not exhibitzero is satisfied and the comparator 1107 indicates the continuity ofthe ID information, it is possible to construct an optical disk drivecapable of carrying out not only a passive operation in which adefective sector processing is performed in response to the defectivesector information from the control microcomputer 108, but also anactive defective sector processing in which the optical disk drivedetects a defective sector and gives to the control microcomputer 108 aninstruction.

[0230] As described above, according to this embodiment, since theinformation of the replay data of the optical disk is analyzed, and thetranslation into the absolute address in the buffer memory is carriedout according to the information acquired by the analysis, the replaydata of the optical disk can be stored into a proper region in thebuffer memory, and since the presence of the information acquired by theanalysis, number of defective sectors, and address of the defectivesector can be detected, the active defective sector processing can beperformed.

[0231] Consequently, in data replay of an optical disk with a scratch,fingerprint or the like, the replay data can be stored into the buffermemory more accurately than before, and in replay of an optical diskwith a defective sector, the burden of the defective sector managementprocessing placed on the control microcomputer can be reduced comparedto the prior art.

[0232] Thus, it is possible to provide an excellent optical disk drivethat can accurately store the data of the optical disk with a scratch,fingerprint, or defective sector into the buffer memory, and reduce theburden of the defective sector management processing placed on thecontrol microcomputer.

[0233] Here, the address generation means 1202, demodulation processingmeans 1203, and ECC block processing means 1204 constituting thecontroller block 118 of this embodiment are an example of the buffermemory address translation device of the present invention, the ECCblock processing means 1204 of this embodiment is an example of thesector address reliability determination device of the presentinvention, the defective sector detection means 1205 of this embodimentis an example of the defective sector determination device of thepresent invention, the ECC block processing means 1204 of thisembodiment is an example of the ECC block synchronization detectiondevice of the present invention. Furthermore, the demodulationprocessing means 1203 and ECC block processing means 1204 of thisembodiment are an example of the analysis means of the presentinvention, and the address generation means 1202 of this embodiment isan example of the address generation means of the present invention.

[0234] In addition, the ID regeneration block 401 of this embodiment isan example of the sector address information readout means of thepresent invention, the ECC block synchronization interpolation block 403and sector synchronization counter block 404 of this embodiment are anexample of the sector address interpolation means of the presentinvention, the ID reliability determination block 405 of this embodimentis an example of the sector address information reliabilitydetermination means of the present invention, the address reliabilitydetermination condition 613 of this embodiment is an example of thepredetermined criterion of the present invention, and the ID informationof this embodiment is an example of the sector address information ofthe present invention.

[0235] In addition, the frame synchronization code encoding block 3030of this embodiment is an example of the frame synchronization codereadout means of the present invention, the frame synchronization codeencoding register A 501 and frame synchronization code encoding registerB 502 of this embodiment are an example of the storage means of thepresent invention, the frame position detection decoder 503 of thisembodiment is an example of the continuity determination means of thepresent invention, the frame synchronization code arrangement OK counter505 of this embodiment is an example of the counter means of the presentinvention, the frame position detection result adoption determinationcircuit 506 of this embodiment is an example of the frame positiondetermination means of the present invention, the frame positiondetermination condition 513 of this embodiment is an example of thepredetermined condition of the present invention, the framesynchronization counter block 307 of this embodiment is an example ofthe frame position interpolation means of the present invention, and theframe synchronization counter value address translation block 332 ofthis embodiment is an example of the address generation means of thepresent invention.

[0236] In addition, the ID regeneration block 401 of this embodiment isan example of the error detection means of the present invention, theaddress comparator 614 of this embodiment is an example of the sectoraddress continuity determination means of the present invention, theaddress reliability determination condition 613 of this embodiment is anexample of the predetermined set condition of the present invention, theaddress reliability condition determination decoder 603 of thisembodiment is an example of the reliability determination means of thepresent invention.

[0237] In addition, the physical ID retaining register A 1101, physicalID retaining register B 1102, incrementer 1103, subtracter 1104, IDretaining register 1105, incrementer B 1106 of this embodiment are anexample of the continuity detection means of the present invention, thedefective sector detector 1108 of this embodiment is an example of thedefective sector detection means of the present invention, thesubtracter 1104, defective sector detector 1120 of this embodiment arean example of the informing means of the present invention, the physicalID information of this embodiment is an example of the sector physicaladdress information of the present invention, the ID signal of thisembodiment is an example of the sector logical address information ofthe present invention, the physical ID retaining register A 1101 of thisembodiment is an example of the sector physical address informationreadout means of the present invention, the physical ID retainingregister B 1102 of this embodiment is an example of the sector physicaladdress information error detection means of the present invention, theincrementer A 1103 and subtracter 1104 of this embodiment are an exampleof the sector physical address information comparison means of thepresent invention, the ID retaining register 1105 of this embodiment isan example of the sector logical address information readout means ofthe present invention, the ID retaining register 1105 of this embodimentis an example of the sector logical address information error detectionmeans of the present invention, and the incrementer B 1106 andcomparator 1107 of this embodiment are an example of the sector logicaladdress information comparison means of the present invention.

[0238] In addition, the ID regeneration block 401 of this embodiment isan example of the error detection means of the present invention, theaddress comparator B 602 of this embodiment is an example of the sectoraddress division means of the present invention, and the addressreliability condition determination decoder 603, selector 604, IDretaining register 417, and address comparator B 602 of this embodimentare an example of the ECC block detection means of the presentinvention.

[0239] The present invention is a program for making a computerimplement functions of all or part of means (or device, element,circuit, section and the like) of the above-described buffer memoryaddress translation device, sector address information reliabilitydetermination device, defective sector determination device, or ECCblock synchronization detection device of the present invention.

[0240] The present invention is a medium that stores the program formaking a computer implement all or part of the functions of all or partof means (or device, element, circuit, section and the like) of theabove-described buffer memory address translation device, sector addressinformation reliability determination device, defective sectordetermination device, or ECC block synchronization detection device ofthe present invention, the medium being computer-readable, and theread-out program cooperating with the computer to implement thefunctions.

[0241] Here, the “part of means (or device, element, circuit, sectionand the like)” of the present invention refer to some of a plurality ofthose means or part of the functions of one means, and the “part ofsteps (or process, operation, action and the like)” of the presentinvention refer to some of a plurality of those steps or part of theoperations in one step.

[0242] In addition, a computer-readable recording medium having theprogram of the present invention recorded therein is also included inthe present invention.

[0243] In addition, the program of the present invention may be used insuch a manner that it is recorded in a computer-readable recordingmedium and cooperates with a computer.

[0244] In addition, the program of the present invention may be used insuch a manner that it is transmitted through a transmission medium andread by a computer to cooperate with the computer.

[0245] In addition, the recording medium includes ROM, the transmissionmedium includes the Internet, light, radio wave, and acoustic wave.

[0246] In addition, the above-described computer of the presentinvention is not limited strictly to hardware such as a CPU and may befirmware or OS and includes peripheral devices.

[0247] Furthermore, as described above, the present invention may beconfigured in the form of software or hardware.

INDUSTRIAL APPLICABILITY

[0248] As apparently seen from the above description, according to thepresent invention, it is possible to provide a buffer memory addresstranslation device, a sector address information reliabilitydetermination device, a defective sector determination device, an ECCblock synchronization detection device, an optical disk drive, a medium,and a program in which even if an abnormality occurs in asynchronization detection and interpolation signal due to a factors suchas a fingerprint or scratch, correspondence between pieces of datastored in a buffer memory is not lost.

[0249] Furthermore, according to the present invention, it is possibleto provide a buffer memory address translation device, a sector addressinformation reliability determination device, a defective sectordetermination device, an ECC block synchronization detection device, anoptical disk drive, a medium, and a program in which data can be readfrom an optical disk medium without the need for acquiring defectivesector information from the optical disk medium.

1. A buffer memory address translation device, characterized in that thebuffer memory address translation device comprises: analysis means ofanalyzing a synchronization pattern included in data read from anoptical disk medium and positional data allowing a data position to berecognized included in the data read from said optical disk medium; andaddress generation means of generating an address for storage into abuffer memory based on a result of said analysis, and said read data isstored in a region corresponding to said generated address in saidbuffer memory.
 2. The buffer memory address translation device accordingto claim 1, characterized in that said positional data is sector addressinformation.
 3. The buffer memory address translation device accordingto claim 1, characterized in that said positional data is a framesynchronization code.
 4. The buffer memory address translation deviceaccording to claim 2, characterized in that said analysis meanscomprises: sector address information readout means of reading sectoraddress information included in the data read from said optical diskmedium; sector address information reliability determination means ofdetermining the reliability of said read sector address information;sector address information interpolation means of interpolating saidsector address information for a sector the sector address informationfor which is not determined to be reliable; and sector addressinformation selection means of selecting said sector address informationread by said sector address information readout means or said sectoraddress information interpolated by said sector address informationinterpolation means according to a predetermined criterion, and saidaddress generation means generates an address for storage into saidbuffer memory according to said selected sector address information. 5.The buffer memory address translation device according to claim 4,characterized in that said read sector address information has an errordetection code added thereto, and said determination of reliability isaccomplished by using said added error detection code to detect an errorin said read sector address information.
 6. The buffer memory addresstranslation device according to claim 4, characterized in that saiddetermination of reliability is accomplished by determining continuitybetween said read sector address information and sector addressinformation previously read.
 7. The buffer memory address translationdevice according to claim 4, characterized in that said predeterminedcriterion is a criterion of reliability required by external controlmeans, and said sector address information selection means selects oneof them by analyzing the criterion of reliability required by saidexternal control means and said determination result of said sectoraddress information reliability determination means.
 8. A buffer memoryaddress translation device, characterized in that the buffer memoryaddress translation device comprises: readout means of reading a framesynchronization code added to data read from an optical disk medium;storage means of encoding said read frame synchronization codes andsequentially storing the same therein; frame position digitization meansof digitizing a position of a frame based on an arrangement of saidcodes stored in said storage means; continuity determination means ofdetermining whether said digitized frame positions are continuous;counter means of counting the number of the digitized frame positionsthat are determined to be continuous; frame position determination meansof comparing the number of the continuous frame positions counted bysaid counter means with a threshold that can be set by an externalcontrol means and, if the result of said comparison satisfies apredetermined condition, determining that the value digitized by saidframe position digitization means is a frame position; frame positioninterpolation means of, if the condition is not satisfied in said frameposition determination means, carrying out interpolation based on aprevious frame position for which the condition is satisfied to find aframe position; and address generation means of generating an addressfor storage into a buffer memory based on said frame position found bysaid frame position interpolation means or the frame position determinedby said frame position determination means, and said read data is storedin a region corresponding to said generated address in said buffermemory.
 9. A sector address information reliability determinationdevice, characterized in that the sector address information reliabilitydetermination device comprises: error detection means of detecting anerror of sector address information included in data read from anoptical disk medium and having an error detection code added thereto;sector address information continuity determination means of comparingsaid sector address information currently extracted from said read datawith said sector address information previously extracted to determinethe continuity of said sector address information; and reliabilitydetermination means of determining the reliability of said sectoraddress information based on the result of the error detection for saidsector address information and the result of the continuitydetermination for said sector address information with reference to apredetermined condition set by said external control means.
 10. Inreadout from a rewritable optical disk medium storing sector physicaladdress information that is a physical address of said sector besidessector logical address information included in data, a defective sectordetermination device, characterized in that the defective sectordetermination device comprises: continuity detection means of detectinga position where a difference occurs between the continuity of saidsector physical address information and the continuity of said sectorlogical address information; defective sector detection means of findinga defective sector using said detected difference; and informing meansof informing an external control means of said detected defectivesector.
 11. The defective sector determination device according to claim10, characterized in that said defective sector detection means detectsthe number of said defective sectors and the sector physical addressinformation of a leading one of said defective sectors, and saidinforming means informs of said number of defective sectors and saidsector physical address information of a leading one of said defectivesectors.
 12. The defective sector determination device according toclaim 10, characterized in that said continuity determination meanscomprises: sector physical address information readout means of readingsaid sector physical address information; sector physical addressinformation error detection means of detecting an error of said readsector physical address information; and sector physical addressinformation comparison means of comparing, of the sector physicaladdress information for which an error is not detected by said sectorphysical address information error detection means, current sectorphysical address information with the previous sector physical addressinformation, and said continuity determination means of, if said sectorphysical address information error detection means detects no error insaid read sector physical address information, determining thecontinuity between said read sector physical address information andsaid previous sector physical address information based on the result ofsaid comparison.
 13. The defective sector determination device accordingto claim 10, characterized in that said continuity determination meanscomprises: sector logical address information readout means of readingsaid sector logical address information; sector logical addressinformation error detection means of detecting an error of said readsector logical address information; and sector logical addressinformation comparison means of comparing, of the sector logical addressinformation for which an error is not detected by said sector logicaladdress information error detection means, current sector logicaladdress information with the previous sector logical addressinformation, and said continuity determination means of, if said sectorlogical address information error detection means detects no error insaid read sector logical address information, determining the continuitybetween said read sector logical address information and said previoussector logical address information based on the result of saidcomparison.
 14. The defective sector determination device according toclaim 10, characterized in that said position where a difference occursis a position where there are one or more sectors for which the sectorphysical address information is determined to be continuous between twocontinuous sectors corresponding to the sector address information forwhich said sector address information is determined to be continuous.15. The defective sector determination device according to claim 11,characterized in that said defective sector detection means regards thesector physical address information of the sector for which said sectorlogical address information is not continuous as the sector physicaladdress information of said leading one of the defective sectors. 16.The defective sector determination device according to claim 11,characterized in that said defective sector detection means detects thenumber of sectors for which said sector physical address information isdetermined to be continuous and that exist between the two sectorscorresponding to the sector logical address information determined to becontinuous, and regards said number of detected sectors as said numberof defective sectors.
 17. An ECC block synchronization detection device,characterized in that the ECC block synchronization device comprises:error detection means of detecting an error of sector addressinformation that is read from an optical disk medium in which an errorcorrecting code is added thereto across n sectors (n=integer) and theerror correcting code is accommodated in the continuous n sectors;sector address information division means of, if said error detectionmeans detects no error in said read sector address information, findingthe quotient of said read sector address information divided by thenumber of sectors constituting an ECC block; and ECC block detectionmeans of, if said sector address information error detection meansdetects no error in said read sector address information, comparing saidquotient of said read sector address information with the previouslyfound quotient and determining that the ECC block synchronization isdetected if the comparison does not result in a match.
 18. An opticaldisk drive, characterized in that the optical disk drive comprises: datareadout means of reading data from an optical disk medium; and acontroller that, in response to a request from an external device,controls said data readout means to temporarily store said read datainto a buffer memory and then transfers the same to said externaldevice, and said controller has the buffer address translation device,sector address reliability determination device, defective sectordetermination device, or ECC block synchronization detection deviceaccording to any of claims 1 to 17 implemented therein.
 19. A mediumcapable of being processed by a computer, characterized in that themedium stores a program for making the computer serve as whole or partof the analysis means of analyzing a synchronization pattern included indata read from an optical disk medium and positional data allowing adata position to be recognized included in the data read from saidoptical disk medium, and the address generation means of generating anaddress for storage into a buffer memory based on a result of saidanalysis of the buffer memory address translation device according toclaim
 1. 20. A medium capable of being processed by a computer,characterized in that the medium stores a program for making thecomputer serve as whole or part of the readout means of reading a framesynchronization code added to data read from an optical disk medium, thestorage means of encoding said read frame synchronization codes andsequentially storing the same therein, the frame position digitizationmeans of digitizing a position of a frame based on an arrangement ofsaid codes stored in said storage means, the continuity determinationmeans of determining whether said digitized frame positions arecontinuous, the counter means of counting the number of the digitizedframe positions that are determined to be continuous, the frame positiondetermination means of comparing the number of the continuous framepositions counted by said counter means with a threshold that can be setby an external control means and, if the result of said comparisonsatisfies a predetermined condition, determining that the valuedigitized by said frame position digitization means is a frame position,the frame position interpolation means of, if the condition is notsatisfied in said frame position determination means, carrying outinterpolation based on a previous frame position for which the conditionis satisfied to find a frame position, and the address generation meansof generating an address for storage into a buffer memory based on saidframe position found by said frame position interpolation means or theframe position determined by said frame position determination means ofthe buffer memory address translation device according to claim
 8. 21. Amedium capable of being processed by a computer, characterized in thatthe medium stores a program for making the computer serve as whole orpart of the error detection means of detecting an error of sectoraddress information included in data read from an optical disk mediumand having an error detection code added thereto, the sector addressinformation continuity determination means of comparing said sectoraddress information currently extracted from said read data with saidsector address information previously extracted to determine thecontinuity of said sector address information, and the reliabilitydetermination means of determining the reliability of said sectoraddress information based on the result of the error detection for saidsector address information and the result of the continuitydetermination for said sector address information with reference to apredetermined condition set by said external control means of the sectoraddress information reliability determination device according to claim9.
 22. A medium capable of being processed by a computer, characterizedin that the medium stores a program for making the computer serve aswhole or part of the continuity detection means of detecting a positionwhere a difference occurs between the continuity of said sector physicaladdress information and the continuity of said sector logical addressinformation, the defective sector detection means of finding a defectivesector using said detected difference, and the informing means ofinforming an external control means of said detected defective sector ofthe defective sector determination device according to claim 10 inreadout from a rewritable optical disk medium storing said sectorphysical address information that is a physical address of said sectorbesides said sector logical address information included in data.
 23. Amedium capable of being processed by a computer, characterized in thatthe medium storing a program for making the computer serve as whole orpart of the error detection means of detecting an error of sectoraddress information that is read from an optical disk medium and has anerror correcting code added thereto across n sectors (n=integer) and theerror correcting code accommodated in the continuous n sectors, thesector address information division means of, if said error detectionmeans detects no error in said read sector address information, findingthe quotient of said read sector address information divided by thenumber of sectors constituting an ECC block, and the ECC block detectionmeans of, if said sector address information error detection meansdetects no error in said read sector address information, comparing saidquotient of said read sector address information with the previouslyfound quotient and determining that the ECC block synchronization isdetected if the comparison does not result in a match of the ECC blocksynchronization detection device according to claim
 17. 24. A programfor making the computer serve as whole or part of the analysis means ofanalyzing a synchronization pattern included in data read from anoptical disk medium and positional data allowing a data position to berecognized included in the data read from said optical disk medium, andthe address generation means of generating an address for storage into abuffer memory based on a result of said analysis of the buffer memoryaddress translation device according to claim
 1. 25. A program formaking the computer serve as whole or part of the readout means ofreading a frame synchronization code added to data read from an opticaldisk medium, the storage means of encoding said read framesynchronization codes and sequentially storing the same therein, theframe position digitization means of digitizing a position of a framebased on an arrangement of said codes stored in said storage means, thecontinuity determination means of determining whether said digitizedframe positions are continuous, the counter means of counting the numberof the digitized frame positions that are determined to be continuous,the frame position determination means of comparing the number of thecontinuous frame positions counted by said counter means with athreshold that can be set by an external control means and, if theresult of said comparison satisfies a predetermined condition,determining that the value digitized by said frame position digitizationmeans is a frame position, the frame position interpolation means of, ifthe condition is not satisfied in said frame position determinationmeans, carrying out interpolation based on a previous frame position forwhich the condition is satisfied to find a frame position, and theaddress generation means of generating an address for storage into abuffer memory based on said frame position found by said frame positioninterpolation means or the frame position determined by said frameposition determination means of the buffer memory address translationdevice according to claim
 8. 26. A program for making the computer serveas whole or part of the error detection means of detecting an error ofsector address information included in data read from an optical diskmedium and having an error detection code added thereto, the sectoraddress information continuity determination means of comparing saidsector address information currently extracted from said read data withsaid sector address information previously extracted to determine thecontinuity of said sector address information, and the reliabilitydetermination means of determining the reliability of said sectoraddress information based on the result of the error detection for saidsector address information and the result of the continuitydetermination for said sector address information with reference to apredetermined condition set by said external control means of the sectoraddress information reliability determination device according to claim9.
 27. A program for making the computer serve as whole or part of thecontinuity detection means of detecting a position where a differenceoccurs between the continuity of said sector physical addressinformation and the continuity of said sector logical addressinformation, the defective sector detection means of finding a defectivesector using said detected difference, and the informing means ofinforming an external control means of said detected defective sector ofthe defective sector determination device according to claim 10 inreadout from a rewritable optical disk medium storing said sectorphysical address information that is a physical address of said sectorbesides said sector logical address information included in data.
 28. Aprogram for making the computer serve as whole or part of the errordetection means of detecting an error of sector address information thatis read from an optical disk medium and has an error correcting codeadded thereto across n sectors (n=integer) and the error correcting codeaccommodated in the continuous n sectors, the sector address informationdivision means of, if said error detection means detects no error insaid read sector address information, finding the quotient of said readsector address information divided by the number of sectors constitutingan ECC block, and the ECC block detection means of, if said sectoraddress information error detection means detects no error in said readsector address information, comparing said quotient of said read sectoraddress information with the previously found quotient and determiningthat the ECC block synchronization is detected if the comparison doesnot result in a match of the ECC block synchronization detection deviceaccording to claim 17.